This invention relates to semiconductor formation, and in particular to gate structure formation in MOSFET devices.
One trend in the semiconductor industry is to make semiconductor devices as small as possible. Often, however, process technology, or the methods used in forming many devices, impose limitations on how small a device can be made.
A typical semiconductor device and a primary building block in the semiconductor industry is the metal oxide semiconductor field effect transistor (MOSFET). A cross-section of a MOSFET is shown in FIG. 1. A MOSFET is typically composed of a gate 106 and an insulating gate layer 104, both formed over silicon substrate 102. Gate 106 is usually composed of polysilicon. Within substrate 102 are formed deep source-drain regions 108 (sometime referred to as heavily doped source and drain regions) and source-drain extension regions 110 (sometimes referred to as lightly-doped source and drain regions. Generally, doped regions are regions containing a higher concentration of p-type or n-type dopants than the rest of the substrate. Source-drain extension regions 130 generally have a lower concentration of dopants compared to deep source-drain regions 150 although some technologies allow the regions to be doped at equivalent levels. The region in the substrate directly below the gate 106 is typically referred to as channel region 112.
Referring to the cross-sections shown in FIG. 2, a brief explanation of the formation of a MOSFET device is given. In FIG. 2A, substrate 102 is doped, by ion implantation or other doping techniques. The doping in FIG. 2A is used to control the characteristics of the channel region 112. After the channel implant, an oxide layer 104 is grown or deposited, over which oxide layer is formed polysilicon layer 106, as shown in FIG. 2B. In FIG. 2C, layers 104 and 106 are patterned and etched leaving a gate stack formation 107. Source-drain extension regions 110 are next formed by introducing dopants into the substrate on either side of the gate stack 107, often with an ion implantation technique, as shown in FIG. 2D. Once the extension regions 110 have been implanted, a spacer forming material 114, such as oxide, is deposited over the entire structure as shown in FIG. 2E. Spacer forming material 114 is then anisotropically etched to form spacers 116 abutting the sidewalls of gate stack 107, FIG. 2F. In FIG. 2G, following the formation of spacers 116, deep source-drain regions 108 are formed, often using ion implantation.
In reducing the size of MOSFET devices, much of the focus has been on reducing the length L of the gate 106. The smallest gate lengths that can be achieved using the process described with respect to FIG. 2 are limited by the lithographic techniques used.
To be able to achieve a gate length that is smaller than that which can be produced using solely lithographic techniques, the technique in FIG. 3 has been utilized, a so-called xe2x80x9cinversexe2x80x9d process. As shown in FIG. 3A, a channel implant is performed, similar to that done in FIG. 2A, to form channel region 312. In FIG. 3B, a sacrificial layer 304 such as nitride is grown or deposited. In FIG. 3C, layer 304 is patterned and etched to form a groove 306. Following groove formation, in FIG. 3D a spacer formation layer 308, such as oxide, is formed over the structure and then anisotropically etched to form spacers 310 shown in FIG. 3E. In FIG. 3F, an oxide layer 314 is grown or deposited at the bottom of the exposed portion of groove 306. In FIG. 3G, a gate material layer 316, such as polysilicon is deposited over the structure, and then a planarization technique, such as a chemical-mechanical polish (CMP), is used to planarize the structure as shown in FIG. 3H. Subsequently, in FIG. 3I, spacers and sacrificial layer 304 are removed leaving gate 316. Once gate 316 has been formed, the steps described with respect to FIGS. 2D-2G would be followed in forming a MOSFET device.
The technique described in FIG. 3 allows a gate to be made slightly smaller than that defined by the minimum gate length permitted by a straight lithographic process. The smallest gate length permitted by the process of FIG. 3 is equal to Lmin minus two times the spacer width (Lminxe2x88x92(2xc3x97spacer width)), where Lmin is the smallest feature dimension achievable with the lithographic process utilized. Even using the techniques of FIG. 3, the smallest gate lengths that have been achieved have been only approximately 0.18 xcexcm.
Forming smaller and more reliable devices also depends on the doping techniques utilized. Using current techniques, however, while control can be had of the type of dopants and the depth of their implant, only limited control exits as to localizing their placement. Referring to FIG. 2, as shown in FIG. 2A, channel doping occurs not only in what will ultimately form the channel region, but also occurs throughout the surface of the substrate 102. As well, source-drain extension region implants, FIG. 2D, are masked by the gate, and hence form doped regions immediately adjacent to the gate, but these regions also extend to the right and left across the exposed substrate region.
Further, it is often desirable to implant dopants underneath the gate region 106. Such implants can only currently be achieved using an angled implant. Nonetheless, this implant is still not localized, i.e., it will still extend into the regions that will become the deep source-drain regions.
To overcome the limitations described above, a method in accordance with the invention has been devised that allows a gate structure to be formed smaller than 0.18 xcexcm despite limitations in the lithographic process. In accordance with the invention, gate structures can be found that are defined by the size of a spacer. Hence, rather than limitations in the lithographic process defining the smallest feature dimensions, spacer dimensions define the smallest features. Using a process in accordance with the invention, gates having a length L on the order of 100 xc3x85 can be achieved.
More specifically one embodiment of a method in accordance with the invention forms a sidewall material over a substrate, the sidewall material having a sidewall. A spacer is formed abutting said sidewall. Subsequently, a second material is formed adjacent to the spacer. In one embodiment the second material is the same as the sidewall material. The spacer is then removed, forming a groove between the sidewall material and the second material. The groove is filled with the material to be used to form a narrow feature, such as a gate. The sidewall material and second material are then removed, leaving a resulting narrow feature.
Further, a method in accordance with the invention has been devised that allows for forming localized doped regions in a substrate. Specifically one embodiment of a method in accordance with the invention forms a sidewall material having a groove formed therein, the groove being defined on either side by a sidewall. Spacers are formed abutting the sidewalls. Subsequently a mid-region material is formed in the groove adjacent to the spacers. The spacers are removed resulting in a pair of grooves. An implant is performed through the grooves, resulting in a localized implant.
In one embodiment, the mid-region material is formed of polysilicon. After forming localized implanted regions, the sidewall material is removed. The result is a semiconductor device with a polysilicon gate having localized implanted regions to either side of the gate edges. In one embodiment such localized implanted regions can form source-drain extensive regions.
In another embodiment of the invention, mid-region material is sacrificial and is removed following the localized implant. A gate material is then placed in the re-formed groove defined by the sidewall material. Once the gate material is in place, the sidewall material is removed. The result is a semiconductor device having localized implanted regions underneath the gate. Such localized implanted regions may be used in some embodiments to control channel characteristics.